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1 of 17 072701 features single 5-bit, prog rammable, pulse-width modulator (pwm) adjustable duty cycle: 0% to 100% 2.7v to 5.5v operation standard frequency values: 1khz, 5khz, 10khz, and 25khz 2-wire addressable interface packages: 8-pin (150-mil) soic and 8-pin (118-mil) sop operating temperature: -40 o c to +85 o c ordering information ds1050z-001 1khz 8-pin 150-mil soic ds1050z-005 5khz 8-pin 150-mil soic ds1050z-010 10khz 8-pin 150-mil soic ds1050z-025 25khz 8-pin 150 mil soic ds1050u-001 1khz 8-pin 118-mil sop ds1050u-005 5khz 8-pin 118-mil sop ds1050u-010 10khz 8-pin 118-mil sop ds1050u-025 25khz 8-pin 118-mil sop pin assignment pin description v cc - 2.7v to 5.5v power supply pwm o - pwm ouput a0, a1, a2 - device address sda - serial data i/o scl - serial clock input gnd - ground description the ds1050 is a programmable, 5-bit, pulse-width m odulator featuring a 2-wire addressable controlled interface. the ds1050 operates from power supplie s ranging from 2.7v up to 5.5v. the pwm output provides a signal that swings from 0v to v cc . the ds1050 requires a typical operating current of 50 a and a programmable shutdown supply current of 1 a. four standard pwm output frequencies are offere d and include 1khz, 5khz, 10khz, and 25khz. the 2-wire addressable interface allows operation of multiple devices on a single 2-wire bus and provides compatibility with other da llas semiconductor 2-wire devices such as real-time clocks (rtcs), digital thermometers, and digital potentiometers. the device is ideal for low-cost lcd contrast and/or brightness control, power supply voltage adjustment, and battery charging or current adjus tment. the ds1050 is offered in standard integrated circuit packaging including the 8-pin (150- mil) soic and space-sa ving 8-pin (118-mil) sop. scl sda a 0 a 1 a 2 v cc gnd pwm 6 7 8 5 3 2 1 4 8-pin 150-mil soic 8-pin 118-mil sop ds1050 5-bit, programmable, pulse- width modulator: 1khz, 5khz, 10khz, and 25khz www.maxim-ic.com
ds1050 2 of 17 operation interface protocol is simplified to an 8-bit control by te and 8-bit data byte. in formation can be read or written to the ds1050 including a commanded shutdown operation. power-up configuration the ds1050 powers-up to half-scale (10000b) providi ng 50% duty-cycle. in this mode, the ds1050 can be used as a standalone oscillator of the frequency specified. once powered, the pwm output can be changed via the 2-wire addressable serial port. pin description v cc ? power supply terminal. the ds1050 will suppor t operation from power supply voltages ranging from +2.7 volts to +5.5 volts. gnd ? ground terminal. pwm o ? pulse-width modulated output. this output is a square-wave having amplitudes from 0 volts to v cc . the duty cycle of this output is governed by a 5- bit control register. output duty cycles range from 0% to 96.88%. an additional command sequence will provide a 100% duty cycle or ?full-on.? scl ? serial clock input. sda ? serial bi-directional data i/o. a0, a1, a2 ? device address (chip selects). 2-wire addressable serial port control the 2-wire serial port interface supports a bi-dir ectional data transmissi on protocol with device addressing. a device that sends data on the bus is defined as a transmitter, and a device receiving data as a receiver. the device that controls the message is called a ?master.? the devices that are controlled by the master are ?slaves.? the bus must be controlled by a master device that generates the serial clock (scl), controls the bus access, and generates the start and stop conditions. the ds1050 operates as a slave on the 2-wire bus. connections to the bus are made via the open-drain i/o lines sda and scl. the following i/o terminals control the 2-wire seri al port: sda, scl, a0, a1, and a2. a 2-wire serial port overview and timing diagrams for the 2-wire serial port can be found in figures 2 and 5, respectively. timing information for the 2-wire serial port is provided in the ?ac electrical characteristics? table for 2-wire serial communications.
ds1050 3 of 17 the following bus protocol has been defined (see figure 2). data transfer may be initiated only when the bus is not busy. during data transfer, the data line must remain stable whenever the clock line is high. changes in the data line while the clock line is high will be interpreted as control signals. accordingly, the following bus conditions have been defined: bus not busy: both data and clock lines remain high. start data transfer: a change in the state of the data line from high to low while the clock is high, defines a start condition. stop data transfer: a change in the state of the data line from low to high while the clock line is high defines the stop condition. data valid: the state of the data line represents valid data when, after a star t condition, the data line is stable for the duration of the high period of th e clock signal. the data on the line must be changed during the low period of the clock signal. there is one clock pulse per bit of data. figure 2 details how data transfer is accomplished on the 2-wire bus. de pending upon the state of the r/w bit, two types of data transfer are possible. each data transfer is initiated with a start c ondition and terminated with a stop condition. the number of data bytes transferred between start and stop conditions is not limited and is determined by the master device. the information is transfer red byte-wise and each receiver acknowledges with a ninth bit. within the bus specifications, a regular mode (100kh z clock rate) and a fast mode (400khz clock rate) are defined. the ds1050 works in both modes. acknowledge: each receiving device, when addressed, is obliged to generate an acknowledge after the reception of each byte. the master device must generate an extra clock pulse that is associated with this acknowledge bit. a device that acknowledges must pull down the sda lin e during the acknowledge clock pulse in such a way that the sda line is stable low during the high period of the acknowledge-related clock pulse. of course, setup and hold times must be taken into account . a master must signal an end of data to the slave by not generating an acknowledge bit on the last byte th at has been clocked out of the slave. in this case, the slave must leave the data line high to enable the master to generate the stop condition. 1. data transfer from a master transmitter to a slave receiver. the first byte transmitted by the master is the command/control byte. next follows a number of data bytes. the slave returns an ?acknowledge? bit after each received byte. 2. data transfer from a slave transmitter to a master receiver. the first byte (the command/control byte) is transmitted by the master. the slave then returns an acknowledge bit. next follows a number of data bytes transmitted by the sl ave to the master. the master re turns an acknowledge bit after all received bytes other than the last byte. at the e nd of the last received byte, a ?not acknowledge? is returned.
ds1050 4 of 17 the master device generates all serial clock pulse s and the start and stop conditions. a transfer is ended with a stop condition or with a repeated start condition. since a repeated start condition is also the beginning of the next serial transfer, the bus will not be released. the ds1050 may operate in the following two modes: 1. slave receiver mode : serial data and clock are received through sda and scl, respectively. after each byte is received, an acknowledge bit is tr ansmitted. start and stop conditions are recognized as the beginning and end of a serial transfer. a ddress recognition is performed by hardware after reception of the slave (device) address and direction bit. 2. slave transmitter mode : the first byte is received and handled as in the slave receiver mode. however, in this mode the direction bit will indicate that the transfer direction is reversed. serial data is transmitted on sda by the ds1050 while the se rial clock is input on scl. start and stop conditions are recognized as the begi nning and end of a serial transfer. slave address a command/control byte is the first byte recei ved following the start condition from the master device. the command/control byte consists of a f our-bit control code. for the ds1050, this is set as 0101 binary for read/write operations. the next three bits of the command/control byte are the device select bits or slave address (a2, a1, a0). they are used by the master device to select which of eight possible devices is to be accessed. when reading or writing the ds1050, the device select bits must match the device select pins (a2, a1, a0). the last bit of th e command/control byte (r/w) defines the operation to be performed. when set to a one a read operation is selected, and when set to a zero a write operation is selected. the command control byte is presented in figure 3. following the start condition, the ds1050 monitors th e sda bus checking the device type identifier being transmitted. upon receiving the 0101 control code , the appropriate device address bits, and the read/write bit, the slave device outputs an ?acknowledge? signal on the sda line. command and protocol the command and protocol structure of the ds1050 allows the user to read or write the pwm configuration register or place the device in a lo w-current state (shut-down mode) and recall the device from a low-current state. additionally, the 2-wire command/protocol structure of the ds1050 will support eight different devices that can be uniquely controlled. figure 4a, b, c, d, & e show the five different command and protocol bytes for the ds1050. these include the following command operations: 1) set pwm dut y cycle, 2) set pwm duty cycle 100%, 3) set shutdown mode, 4) set re call mode, 5) read pwm configuration register. the command operation ?set pwm duty cycle? is used to configure the output duty cycle of the device. the ds1050 has a 5-bit resolution and is capable of setting the duty cycle output from 0% up to 96.88% in steps of 3.125%. a binary value of (00000b) sets the duty cycle output at 0% while a binary value of (11111b) sets the duty cycle output at 96.88%. the command operation ?set pwm duty cycle 100%? is used to configure the output duty cycle of the device to a ?full-on.? this command is provided in addition to the set pwm duty cycle command for flexibility and convenience in total duty cycle coverage. it allows the user to provide a total duty cycle range from 0% to 100%.
ds1050 5 of 17 the command operation ?set shutdown m ode? is used to provide a low-current (inactive state) state for the ds1050. when in a low-current state the ds1050 will draw currents less than or equal to 1 a. the pwm o output will be high impedance. the command operation ?set recall mode? is used to recall the ds1050 from a low-current state. the value of the pwm o output is recalled to that prior to initiating a ?set shutdown mode? command. the ?read pwm duty cycle? command is used to r ead the current setting of the pwm configuration register. information returned by this command incl udes pwm output value as well as whether the device is in a shutdown configuration. pwm data values and control/command values are always transmitted most significant bit (msb) first. during communications, the receiving un it always generates the ?acknowledge.? reading the ds1050 as shown in figure 4e, the ds1050 provides one read command operation . this operation allows the user to read the current setting of the pwm configuration register. specifically, the r/w bit of the command/control byte is set equal to a 1 for a r ead operation. communication to read the ds1050 begins with a start condition which is issued by the master device. the command/control byte from the master device will follow the start condition. on ce the command/control byte has been received by the ds1050, the part will respond with an acknowledg e. the read/write bit of the command/control byte, as stated, should be set equal to 1 for reading the ds1050. when the master has received the acknowledge from the ds1050, the master can then begin to receive the pwm configuration register data. as men tioned this data will be tr ansmitted msb first. once the eight bits of the pwm configuration register have been transmitted, the master will need to issue an acknowledge, unless it is the only byte to be read, in which case the master issues a not acknowledge. if desired the master may stop the comm unication transfer at this point by issuing the stop condition. final communication transfer is terminated by issuing the stop command. again, the flow of the read operation is presented in figure 4e. writing the ds1050 a data flow diagram for writing the ds1050 is show n in figures 4a, b, c, and d. the ds1050 has three write commands that are used to change the pwm c onfiguration register or the shutdown and recall mode of the device. all the write operations begin with a start c ondition. following the start condition, the master device will issue the command/control byte. the read/write bit of the command/control byte will be set to ?0? for writing the ds1050. once the command/control byte has been issued and the master receives the acknowledgment from the ds1050, pwm configuration data is trans mitted to the ds1050 by the master device. a data byte for the ds1050 will contain pwm conf iguration data and shut down/recall command data. the five least significant bits of data specify the pwm configuration value while the three most significant bits specify the whether the device is to be shutdown or recalled. when the ds1050 has received the data byte, it will respond with an acknowledge. at this point, the new pwm configuration register value and shutdown/reca ll command value will be updated in the ds1050. the master device, after the receipt of the acknowledge, can continue to transmit additi onal data bytes
ds1050 6 of 17 or if the transaction is comple te respond with the stop condition. the 2-wire serial timing diagram is presented in figure 5.
ds1050 7 of 17 absolute maximum ratings* voltage on any pin relativ e to ground -0.3v to +6.0v operating temperature -40 o c to +85 o c storage temperature -55 o c to +125 o c soldering temperature see j-std-020a specification * this is a stress rating only and f unctional operation of the device at these or any other conditions above those conditions indicated in the operation secti on of the specification is not implied. exposure to absolute maximum rating conditions for extended periods of time may affect reliability. recommended dc operating conditions (-40 c to +85 c; v cc = 2.7v to 5.5v) parameter symbol min typ max units notes supply voltage v cc +2.7 +5.5 v 1 dc electrical characteristics (-40 c to +85 c; v cc = 2.7v to 5.5v) parameter symbol condition min typ max units notes active supply current i cc 50 85 a 2 input leakage i li +1 a input logic 1 v ih 0.7 v cc v cc +0.3 v 3, 4 input logic 0 v il gnd-0.3 0.3 v cc v 3, 4 input current each i/o pin 0.4 v i/o 0.9 v cc -10 10 a standby current i stby 0.1 1 a 5 low level ouput voltage (sda) v ol1 v ol2 3ma sink current 6ma sink current 0.0 0.0 0.4 0.6 v v i/o capacitance c i/o 10 pf pwm output currents i oh i ol v cc - 0.4 0.4 2 3 ma ma
ds1050 8 of 17 ac electrical characteristics (-40 c to +85 c; v cc = 2.7v to 5.5v) parameter symbol condition min typ max units notes scl clock frequency f scl fast mode standard mode 0 0 400 100 khz 6 bus free time between stop and start condition t buf fast mode standard mode 1.3 4.7 s 6 hold time (repeated) start condition t hd:sta fast mode standard mode 0.6 4.0 s 7, 6 low period of scl clock t low fast mode standard mode 1.3 4.7 s 6 high period of scl clock t high fast mode standard mode 0.6 4.0 s 6 data hold time t hd:dat fast mode standard mode 0 0 0.9 s 6, 8, 9 data set-up time t su:dat fast mode standard mode 100 250 ns 6 rise time of both sda and scl signals t r fast mode standard mode 20+0.1c b 300 1000 ns 10 fall time of both sda and scl signals t f fast mode standard mode 20+0.1c b 300 300 ns 10 set-up time for stop condition t su:sto fast mode standard mode 0.6 4.0 s capacitive load for each bus line cb fast mode standard mode 400 pf 10 pwm output change t pwm fast mode standard mode 2 periods 11 ac electrical characteristics (-40 c to +85 c; v cc = 2.7v to 5.5v) parameter symbol condition min typ max units notes output frequency tolerance -20 +20 % 12 output impedance 200 absolute linearity -0.5 +0.5 lsb 14 relative linearity -0.25 +0.25 lsb 15 resolution 5 bits 13 frequency temperature coefficient 200 ppm/oc frequency voltage coefficient 1.5 % per v
ds1050 9 of 17 notes: 1. all voltages are referenced to ground. 2. i cc specified with outputs open. 3. i/o pins of fast mode devices must not obstruct the sda and scl lines if v cc is switched off. 4. address inputs, a0, a1, and a 2, should be tied to either v cc or gnd depending on the desired address selections. 5. i stby specified for v cc between 3.0v and 5.0v, control port logic pins are driven to the appropriate logic levels. 6. a fast mode device can be used in a standard mode system, but the requirement t su:dat > 250ns must then be met. this will automati cally be the case if the device does not stretch the low period of the scl signal. if such a de vice does stretch the low period of the scl signal, it must output the next data bit to the sda line t rmax + t su:dat = 1000 + 250=1250ns before the scl line is released. 7. after this period, the first clock pulse is generated. 8. the maximum t su:dat has only to be met if the devi ce does not stretch the low period (t low ) of the scl signal. 9. a device must internally provide a hold time of at least 300ns for the sda signal (referred to the v ih min of the scl signal) in order to bridge the undefined region of the falling edge of scl. 10. c b ? total capacitance of one bus line in picofarads, timing referenced to (0.9)(v cc ) and (0.1)(v cc ). 11. a pwm output duty cycle change will occur with 2 periods of the output frequency when a change is initiated. 12. the absolute frequency output of the pwm can be expected to fall within a 20% range from the nominal specified value of the device. 13. the ds1050 is a 5-bit pwm. the output duty cycles of the device range from 0% to 100% in step sizes of 3.125%. the ?set pwm duty cycle 100%? allows the pwm output to be set to full-on. 14. absolute linearity is used to compare measured duty cycle against expected duty cycle as determined by the dac setting. the ds1050 is sp ecified to provide an absolute linearity of 0.5 lsb. 15. relative linearity is used to determine the change in duty cycle between adjacent or successive duty cycle settings. the ds1050 is specified to pr ovide a relative linearity specification of 0.25 lsb.
ds1050 10 of 17 block diagram figure 1 2-wire addressable serial port overview figure 2 repeated if more bytes are transferred acknowledgement signal from receiver scl sda 12 678 ack slave address start condition 9 stop condition or repeated start conditi on acknowledgement signal from receiver 9 1 2 8 3-7 ack r/w direction bit msb command/control byte figure 3 serial port control logic oscillator scl a2 a1 a0 sda driver v cc gnd shutdown control circuitry pwm device identifie r device a ddress read/write bit 1 a 1 a 0 0 0 a 2r/w 1 msb lsb
ds1050 11 of 17 ds1050 commands and protocol figure 4 msb lsb s t a r t a0 a1 a2 1 0 1 00 r/w=0 control byte msb lsb pwm databyte 00 don't care 1 msb lsb a0 a1 a2 1 0 1 00 r/w=0 control byte msb lsb pwm databyte 11 don't care 0 set shut-down mode msb lsb a0 a1 a2 1 0 1 01 r/w=1 control byte msb lsb pwm databyte 00 pwm-data 0 read pwm duty cycle msb lsb a0 a1 a2 1 0 1 00 r/w=0 control byte msb lsb pwm databyte 10 don't care 0 recall mode (e) (d) (c) (b) s t a r t s t a r t s t a r t s t a r t s t o p s t o p s t o p s t o p msb lsb s a a0 a1 a2 1 0 1 00 r/w=0 control byte msb lsb pwm databyte 00 pwm data 0 set pwm duty cycle (a) s t a r t s t a r t s t o p a c k a c k a c k a c k a c k
ds1050 12 of 17 2-wire serial diagrams figure 5 t buf scl sda stop start t hd:sta t r t low t hd:sta t high f t t su:dat repeated start t su:sta t hd:sta t sp t su:sto
ds1050 13 of 17 typical operating characteristics ds1050 (v cc = 5.0v; t = +25oc, unless otherwise specified) supply current ( a) ds1050 supply current vs. frequency 10 15 20 25 30 35 40 45 50 55 0 5 10 15 20 25 30 frequency (khz) ds1050 supply current vs freq, 3.3v ds1050 supply current vs freq, 5v duty cycle (%) ds1050 duty cycle vs. position 0 10 20 30 40 50 60 70 80 90 100 0 5 10 15 20 25 30 position setting (decimal) ds1050 duty cycle vs position, 3.3v and 5v
ds1050 14 of 17 typical operating characteristics ds1050-001 (v cc = 5.0v, t = +25oc, unless otherwise specified) ds1050-001 frequency vs. temperature 0.985 0.990 0.995 1.000 1.005 1.010 1.015 1.020 1.025 1.030 -40-20 0 20406080 temperature (c) ds1050-001 freq vs temp, 3.3v ds1050-001 freq vs temp, 5v supply current ( a) ds1050-001 supply current vs. temperature 10 15 20 25 30 35 40 -40-20 0 20406080 temperature (c) ds1050-001 supply current vs temp, 3.3v ds1050 - 001 supply current vs temp 5v
ds1050 15 of 17 typical operating characteristics ds1050-005 (v cc = 5.0v, t = +25oc, unless otherwise specified) ds1050-005 frequency vs. temperature 4.95 5 5.05 5.1 5.15 5.2 -40-20 0 20406080 temperature (c) ds1050-005 freq vs temp, 3.3v ds1050-005 freq vs temp, 5v supply current ( a) ds1050-005 supply current vs. temperature 10 15 20 25 30 35 40 45 -40-20 0 20406080 temperature (c) ds1050-005 supply current vs temp, 3.3v ds1050-005 supply current vs temp, 5v
ds1050 16 of 17 typical operating characteristics ds1050-010 (v cc = 3v, t = +25oc, unless otherwise specified) ds1050-010 frequency vs. temperature 10.3 10.35 10.4 10.45 10.5 10.55 10.6 10.65 10.7 -40 -20 0 20 40 60 80 temperature (c) ds1050-010 freq vs temp, 3.3v ds1050-010 freq vs temp, 5v supply current ( a) ds1050-010 supply current vs. temperature 10 15 20 25 30 35 40 45 50 -40-20 0 20406080 temperature (c) ds1050-010 supply current vs temp, 3.3v ds1050-010 supply current vs temp, 5v
ds1050 17 of 17 typical operating characteristics ds1050-025 (v cc = 5.0v; t = +25oc, unless otherwise specified) ds1050-025 frequency vs. temperature 25.2 25.4 25.6 25.8 26 26.2 26.4 26.6 26.8 -40-200 20406080 temperature (c) ds1050-025 freq vs temp, 3.3v ds1050-025 freq vs temp, 5v supply current ( a) ds1050-025 supply current vs. temperature 10 15 20 25 30 35 40 45 50 55 -40-20 0 20406080 temperature (c) ds1050-025 supply current vs temp, 3.3v ds1050-025 supply current vs temp, 5v
english ? ???? ? ??? ? ??? what's new products solutions design appnotes support buy company members ds1050 part number table notes: see the ds1050 quickview data sheet for further information on this product family or download the ds1050 full data sheet (pdf, 240kb). 1. other options and links for purchasing parts are listed at: http://www.maxim-ic.com/sales . 2. didn't find what you need? ask our applications engineers. expert assistance in finding parts, usually within one business day. 3. part number suffixes: t or t&r = tape and reel; + = rohs/lead-free; # = rohs/lead-exempt. more: see full data sheet or part naming conventions . 4. * some packages have variations, listed on the drawing. "pkgcode/variation" tells which variation the product uses. 5. part number free sample buy direct package: type pins size drawing code/var * temp rohs/lead-free? materials analysis ds1050z-025/w soic;8 pin;150 dwg: 56-g2008-001c (pdf) use pkgcode/variation: s8-2 * -40c to +85c rohs/lead-free: no materials analysis ds1050z-010/t&r soic;8 pin;150 dwg: 56-g2008-001c (pdf) use pkgcode/variation: s8-2 * -40c to +85c rohs/lead-free: no materials analysis ds1050z-005/t&r soic;8 pin;150 dwg: 56-g2008-001c (pdf) use pkgcode/variation: s8-2 * -40c to +85c rohs/lead-free: no materials analysis
ds1050z-001/t&r soic;8 pin;150 dwg: 56-g2008-001c (pdf) use pkgcode/variation: s8-4 * -40c to +85c rohs/lead-free: no materials analysis ds1050z-010+ soic;8 pin;150 dwg: 56-g2008-001c (pdf) use pkgcode/variation: s8+4 * -40c to +85c rohs/lead-free: yes materials analysis ds1050z-025/t&r soic;8 pin;150 dwg: 56-g2008-001c (pdf) use pkgcode/variation: s8-2 * -40c to +85c rohs/lead-free: no materials analysis ds1050z-010+t&r soic;8 pin;150 dwg: 56-g2008-001c (pdf) use pkgcode/variation: s8+4 * -40c to +85c rohs/lead-free: yes materials analysis ds1050z-005+t&r soic;8 pin;150 dwg: 56-g2008-001c (pdf) use pkgcode/variation: s8+4 * -40c to +85c rohs/lead-free: yes materials analysis ds1050z-025+t&r soic;8 pin;150 dwg: 56-g2008-001c (pdf) use pkgcode/variation: s8+4 * -40c to +85c rohs/lead-free: yes materials analysis ds1050z-005+ soic;8 pin;150 dwg: 56-g2008-001c (pdf) use pkgcode/variation: s8+4 * -40c to +85c rohs/lead-free: yes materials analysis ds1050z-025+ soic;8 pin;150 dwg: 56-g2008-001c (pdf) use pkgcode/variation: s8+4 * -40c to +85c rohs/lead-free: yes materials analysis ds1050z-025 soic;8 pin;150 dwg: 56-g2008-001c (pdf) use pkgcode/variation: s8-2 * -40c to +85c rohs/lead-free: no materials analysis ds1050z-001+t&r soic;8 pin;150 dwg: 56-g2008-001c (pdf) use pkgcode/variation: s8+4 * -40c to +85c rohs/lead-free: yes materials analysis ds1050z-005 soic;8 pin;150 dwg: 56-g2008-001c (pdf) use pkgcode/variation: s8-2 * -40c to +85c rohs/lead-free: no materials analysis
ds1050z-001+ soic;8 pin;150 dwg: 56-g2008-001c (pdf) use pkgcode/variation: s8+4 * -40c to +85c rohs/lead-free: yes materials analysis ds1050z-010 soic;8 pin;150 dwg: 56-g2008-001c (pdf) use pkgcode/variation: s8-2 * -40c to +85c rohs/lead-free: no materials analysis ds1050z-001 soic;8 pin;150 dwg: 56-g2008-001c (pdf) use pkgcode/variation: s8-4 * -40c to +85c rohs/lead-free: no materials analysis ds1050u-025/t&r usop;8 pin;118 dwg: 21-0036j (pdf) use pkgcode/variation: u8-1 * -40c to +85c rohs/lead-free: no materials analysis ds1050u-001/t&r usop;8 pin;118 dwg: 21-0036j (pdf) use pkgcode/variation: u8-1 * -40c to +85c rohs/lead-free: no materials analysis ds1050u-010+t usop;8 pin;118 dwg: 21-0036j (pdf) use pkgcode/variation: u8+1 * -40c to +85c rohs/lead-free: yes materials analysis ds1050u-001+ usop;8 pin;118 dwg: 21-0036j (pdf) use pkgcode/variation: u8+1 * -40c to +85c rohs/lead-free: yes materials analysis ds1050u-001+t usop;8 pin;118 dwg: 21-0036j (pdf) use pkgcode/variation: u8+1 * -40c to +85c rohs/lead-free: yes materials analysis ds1050u-025+ usop;8 pin;118 dwg: 21-0036j (pdf) use pkgcode/variation: u8+1 * -40c to +85c rohs/lead-free: yes materials analysis ds1050u-005+ usop;8 pin;118 dwg: 21-0036j (pdf) use pkgcode/variation: u8+1 * -40c to +85c rohs/lead-free: yes materials analysis ds1050u-025+t usop;8 pin;118 dwg: 21-0036j (pdf) use pkgcode/variation: u8+1 * -40c to +85c rohs/lead-free: yes materials analysis
ds1050u-005+t usop;8 pin;118 dwg: 21-0036j (pdf) use pkgcode/variation: u8+1 * -40c to +85c rohs/lead-free: yes materials analysis ds1050u-010+ usop;8 pin;118 dwg: 21-0036j (pdf) use pkgcode/variation: u8+1 * -40c to +85c rohs/lead-free: yes materials analysis ds1050u-001 usop;8 pin;118 dwg: 21-0036j (pdf) use pkgcode/variation: u8-1 * -40c to +85c rohs/lead-free: no materials analysis ds1050u-005 usop;8 pin;118 dwg: 21-0036j (pdf) use pkgcode/variation: u8-1 * -40c to +85c rohs/lead-free: no materials analysis ds1050u-010 usop;8 pin;118 dwg: 21-0036j (pdf) use pkgcode/variation: u8-1 * -40c to +85c rohs/lead-free: no materials analysis ds1050u-025 usop;8 pin;118 dwg: 21-0036j (pdf) use pkgcode/variation: u8-1 * -40c to +85c rohs/lead-free: no materials analysis didn't find what you need? contact us: send us an email copyright 2007 by maxim integrated products, dallas semiconductor ? legal notices ? privacy policy

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